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d18c7db

Contributor

Registered: 2008-08-19

Posts: 292

FPGA source compilation problem

Do we know who added the 14443a support to the FPGA code? Is he on this forum?

I've been trying to compile the FPGA from source (I know it's not strictly required) using Xilinx's latest webpack and the compilation fails:

ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
   component:
        PAD symbol "pck0" (Pad Signal = pck0)
        BUF symbol "pck0_IBUF" (Output Signal = pck0_IBUF)
   A generic IO component of type IOB was chosen because the IO contains symbols
   and/or properties consistent with input, output, or bi-directional usage and
   contains no other symbols or properties that require a more specific IO
   component type.

I've been tearing my hair out on this as this generic error is not very useful. This seems to be related to the user constraints file, as the source compiles when I remove the pck0 to PIN 36 constraint but of course that is a must since we actually want pck0 to be on PIN36.

Has anyone been able to compile the FPGA source?
What changes to the source were required if any?
What tools and versions did they use?
Any other gotchas?

d18c7db

Contributor

Registered: 2008-08-19

Posts: 292

Re: FPGA source compilation problem

Oh thanks for that pointer SD, it worked so the project compiles now. Weird that JW 's sources compiled without that "fix" even through we're all using Xilinx's compilers.

I've been having some fun with ModelSim-XE and running some of the modules through the simulator and looking at the waveforms. I love ModelSim and this is about as much as I can do untill I actually build my Proxmark hopefully in a couple of weeks. The PCBs are on their way to me as I type from what I heard...

dceliano

Contributor

Registered: 2018-04-23

Posts: 4

Re: FPGA source compilation problem

Hello d18c7cb. It seems like you solved this problem, but the solution is not in this post. Can you please tell me what solution you ended up finding, or can someone else suggest how to fix this error? It seems to be a mapping error in Xilinx.

Thank you in advance.

iceman

Administrator

Registered: 2013-04-25

Posts: 9,538

Website

Re: FPGA source compilation problem

wow,  talk about bringing a dead thread back to life... 10 years..